1. FIELD OF THE INVENTION
The invention relates to a logic control system for providing to a CPU (central processing unit) both instructions and procedural information such as constants, displacements, and addresses stored in a memory system, and more particularly to a logic control system which may accommodate the transfer of information to the CPU without compromising memory system bandwidths or CPU execution speeds, and which further may accomodate the modification of CPU instructions during instruction execution.
2. PRIOR ART
In logic control systems heretofore used in data processing systems, CPU (central processing unit) requests for instructions and procedural information stored in a central memory system incur transfer delays causing the CPU to enter into idle states awaiting either new instructions or procedural information required during the execution of an instruction. More particularly, a logic control system typically is initialized by the CPU to request a bus cycle from a communication bus to which the central memory system is attached. Upon acquiring the bus cycle, the logic control system requests and receives instructions and procedural information such as constants, displacements and addresses from the memory system. Upon the CPU receiving such information from the logic control system, the CPU executes the instructions with reference to the procedural information. The CPU execution speed thus is dependent not only upon internal execution speeds but also upon the information transfer rate between the memory system and the CPU.
The transfer delays have been partially ameliorated by logic systems accommodating block transfers from the central memory system to directly accessible memory systems such as a cache memory system. Please refer to U.S. patent application Ser. No. 221,854 now U.S. Pat. No. 4,424,561 entitled "Odd/Even Bank Structure For A Cache Memory" which is assigned to the assignee of the present invention, and which particularly describes the structure and operation of a cache memory system. The CPU execution speeds, however, still have been limited to an undesirable extent by the transfer delays between the cache memory system and the CPU.
Further deficiencies in prior logic control systems have been the lack of flexibility in performing tasks other than information transfer tasks in providing instructions to the CPU, and the inability to overcome timing variances incurred in transferring instructions to the CPU while accommodating instruction modification during instruction execution.
In the present invention, a hardware/firmware logic control system is provided which accommodates the transfer of not only procedural information but also CPU instructions from a memory system to a CPU at a rate sufficiently high to avoid compromises of either memory bandwidths or CPU execution speeds caused by information transfer delays, and which further accommodates the modification of CPU instructions during instruction execution and the use of logic devices for tasks other than the transfer of information during instruction execution without incurring timing variances in providing the instructions to the CPU.